1. Field of the Invention
The invention relates to data communications, and more particularly, to joint equalizing and decoding of an incoming data stream using a parallel decision-feedback decoder (PDFD).
2. Description of the Prior Art
The IEEE 802.3ab standard for gigabit Ethernet, also termed 1000BASE-T, is now considered the future trend in local area network (LAN) applications. Gigabit Ethernet is defined as able to provide 1 gigabit per second (Gbps) bandwidth in combination with the simplicity of an Ethernet architecture, at a lower cost than other technologies of comparable speed. Moreover, gigabit Ethernet offers a smooth, seamless upgrade path for present 10BASE-T or 100BASE-T Ethernet installations.
In order to obtain the requisite gigabit performance levels, gigabit Ethernet transceivers are interconnected with a multi-pair transmission channel architecture. In particular, transceivers are interconnected using four separate pairs of twisted Category-5 copper wires. Gigabit communication, in practice, involves the simultaneous, parallel transmission of information signals, with each signal conveying information at a rate of 250 megabits per second (Mb/s).
In particular, the gigabit Ethernet standard requires that digital information being processed for transmission be symbolically represented in accordance with a five-level pulse amplitude modulation scheme (PAM-5) and encoded in accordance with an 8-state Trellis coding methodology. Coded information is then communicated over a multi-dimensional parallel transmission channel to a designated receiver, where the original information must be extracted (demodulated) from a multi-level signal. In gigabit Ethernet, it is important to note that it is the concatenation of signal samples received simultaneously on all four twisted pair lines of the channel that defines a symbol. Thus, demodulator/decoder architectures must be implemented with a degree of computational complexity that allows them to accommodate not only the “state width” of Trellis coded signals, but also the “dimensional depth” represented by the transmission channel.
Computational complexity is not the only challenge presented to modern gigabit capable communication devices. A perhaps greater challenge is that the complex computations required to process the incoming signals must be performed in very small period of time. For example, in gigabit applications, each of the four-dimensional signal samples, formed by the four signals received simultaneously over the four twisted wire pairs, must be efficiently decoded within a particular allocated symbol time window of about 8 nanoseconds.
In addition to the challenges imposed by decoding and demodulating multilevel signal samples, transceiver systems must also be able to deal with intersymbol interference (ISI) introduced by transmission channel artifacts as well as by modulation and pulse shaping components in the transmission path of a remote transceiver system. During the demodulation and decoding process of Trellis coded information, ISI components are introduced by either means must also be considered and compensated, further expanding the computational complexity and thus, system latency of the transceiver system. Without a transceiver system capable of efficient, high-speed signal decoding as well as simultaneous ISI compensation, gigabit Ethernet would likely not remain a viable concept.
According to Azadet et al. in the article entitled “A 1-Gb/s Joint Equalizer and Trellis Decoder for 1000BASE-T Gigabit Ethernet” published in the IEEE Journal of Solid-state Circuits, Vol. 3 6, NO. 3, March 2001, which is incorporated herein by reference, a 14-tap parallel decision-feedback decoder (PDFD) is described. As the hardware complexity of the DFU accounts for the majority of the hardware complexity of the PDFD, In order to reduce the hardware complexity of the PDFD, the article proposes using, a 1-tap PDFD having decision-feedback prefilters used for each wire pair to shorten the channel memory to one is also proposed in the article, for the hardware complexity of the DFU accounts for the majority of the hardware complexity of the PDFD. However, the proposed solution significantly increases the bit error rate of the PDFD because only 1-tap is used and therefore the ISI is not effectively removed.